SD decoder for digital communications

ABSTRACT

There is provided an ultra-light decoder for high speed digital communications based on block codes such as turbo product codes (TPCs). The new decoder can perform soft decision decoding without an algebraic hard decision decoder, which is the core of conventional soft decision decoders. The elimination of algebraic decoder significantly reduces the number of computations required per codeword, consequently, it reduces the decoding delay and processing power. However, reducing the decoding delay would immediately enable increasing the transmission speed, and minimize the need for large buffers at the receiver. Moreover, reducing the complexity and delay would enable using codes with high code rates to increase the system capacity, or use powerful codes with low code rates to reduce the transmission power. Such benefits can be achieved for about 1 dB loss in coding gain. There is also provided a receiver comprising the ultra-light decoder, as well as a decoding process.

FIELD OF THE INVENTION

The present invention generally relates to block codes decoders used incommunication systems and more particularly to an improved Soft Decision(SD) decoder for digital communications.

BACKGROUND OF THE INVENTION

Forward error correction (FEC), known also as channel coding, is one ofthe key tools that enabled the massive growth of the wirelesscommunications industry in the last decade. The basic role of FEC is toprovide the users with reliable digital transmission using minimumexcess power, bandwidth and complexity. Consequently, FEC substantiallycontributed to the success of transformation towards the A⁵ vision(anyone to access anything from anywhere at any time on any device).Such vision has placed stringent quality of service (QoS) requirements,which require optimal design at all layers of the wirelesscommunications protocol stack to reduce the cost, power consumption andcomplexity while increasing the capacity, coverage and reliability.Watching high definition television (HDTV) on small-size mobile devicesis an example for such extreme QoS requirements because such applicationrequires up to 34 Mbps with packet error rate less than 10⁻⁶. Theproblem becomes even more challenging when such mobile devices are usedfor transmission. For example, video conferencing requires up to 192Mbps and packet error rate of less than 10⁻⁴.

Turbo Product Codes (TPCs) are currently included in variouscommunication standards such as the IEEE 802.16 for fixed and mobilebroadband wireless access systems, which is commercially known as theWorldwide Interoperability for Microwave Access (WiMAX), IEEE 802.20Mobile Broadband Wireless Access (MBWA) for local and metropolitan areanetworks, and IEEE-1901 for broadband power line networks. Moreover,TPCs have been proposed for many applications such as opticalcommunications, satellite systems, multimedia transmission and datastorage devices.

There are traditionally two types of decoders used for block codes suchas TPCs, Hard Decision (HD) decoders and Soft Decision (SD) decoders. Ascompared to SD decoders, HD decoders have poor performance and lowcomplexity. SD decoders have better performance however they remainhighly complex because they use very large number of HD decoders as partof their overall process and system.

SUMMARY OF THE INVENTION

Therefore, there is an advantage in providing an improved SD decoderwhich does not use HD decoders.

As a first aspect of the present invention, there is provided animproved SD decoder for digital communications configured to decode areceived signal (r) using an improved SD decoding process, the receivedsignal (r) being encoded using block coding, modulated using amodulation technique and transmitted over a communication channelsubject to channel noise, wherein the improved SD decoder comprises abinary multiplier encoder configured to encode data as part of theimproved SD decoding process.

As another aspect of the invention, there is provided a receivercomprising an improved SD decoder for digital communications configuredto decode a received signal (r) using an improved SD decoding process,the received signal (r) being encoded using block coding, modulatedusing a modulation technique and transmitted over a communicationchannel subject to channel noise, wherein the improved SD decodercomprises a binary multiplier encoder configured to encode data as partof the improved SD decoding process.

As a further aspect of the invention, there is provided an improved SDdecoding process for decoding a received signal (r), the received signal(r) being encoded using block coding, modulated using a modulationtechnique and transmitted over a communication channel subject tochannel noise, wherein the improved SD decoding process comprisesencoding data using a binary multiplier encoder as part of the improvedSD decoding process.

Preferably, the improved SD decoder does not include a Hard Decision(HD) decoder and the decoding process does not involve any Hard DecisionDecoding (HDD) operations.

In an embodiment of the invention, the block coding is turbo coding,however any block coding can also work.

Preferably, the received signal (r) is an analog signal comprising atransmitted signal (u) and channel noise (z) such that r=u+z, where thetransmitted vector (u) comprises information data and parity dataexpressed by u=[m₁, m₂, . . . , m_(k), p₁, p₂, . . . , p_(n-k)], wherem_(i) and p_(j) correspond to the information data and parity datarespectively.

Preferably, the improved SD decoding process comprises:

-   -   a) dropping the parity data in the received signal (r) for        forming a new vector r_(1→k), where the new vector r_(1→k)        comprises least reliable q samples having respective indices;    -   b) determining the least reliable q samples in the new vector        r_(1→k), and marking the indices of the least reliable q samples        in r_(1→k) (marked bits);    -   c) computing hard decision bits of r_(1→k);    -   d) generating 2^(q) vectors (error patterns) each of which has k        bits by alternating values of the marked bits between zeros and        ones until all possible 2^(q) combinations are generated;    -   e) generating 2^(q) different test patterns by adding each error        pattern to the hard decision bits computed in (c);    -   f) encoding 2^(q) test patterns to produce 2^(q) candidate        codewords; and    -   g) determining a successful candidate codeword among the        produced 2^(q) candidate codewords, where the successful        candidate is the one that has a minimum Euclidean distance to        the received signal(r).

In an embodiment of the invention, the channel noise is Additive WhiteGaussian Noise (AWGN).

Preferably, the modulation technique is binary phase-shift keying(BPSK), however the invention can work with any other modulationtechnique.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter that is regarded as the invention is particularlypointed out and distinctly claimed in the claims at the conclusion ofthe specification. The foregoing and other aspects, features, andadvantages of the invention are apparent from the following detaileddescription taken in conjunction with the accompanying drawings inwhich:

FIG. 1 illustrates a 2D TPC codeword;

FIG. 2 illustrates a Conventional soft-input soft output (SISO) decoderbased on Chase-II soft decision decoding algorithm;

FIG. 3 illustrates BER of TPC eBCH(16,11,4)²;

FIG. 4 illustrates BER TPC eBCH(32,26,4)²;

FIG. 5 illustrates BER TPC eBCH(64,57,4)²; and

FIG. 6 illustrates BER TPC eBCH(128,120,4)².

DETAILED DESCRIPTION OF THE INVENTION

Overview of the Improved SD Decoder

The present invention relates to an improved SD decoder which is lesscomplex than a traditional SD decoder. The improved SD decoder of thepresent invention does not use an HDD decoder and therefore avoids thecomplexity resulted from using large numbers of such HDD decoders. Theimproved SD decoder of the present invention can be used with any typeof block codes including but not limited to Turbo Product Codes (TPCs).Also, the improved SD decoder of the present invention can be used withany type of digital communication systems, any type of communicationchannels and any type of modulation techniques. Though the improved SDdecoding system will be illustrated in detail hereinafter using TPCs,BPSK and AWGN for block coding, modulation and communication channel, aperson skilled in the art should understand that this is done forexemplary purposes only and should not be used to narrow the scope ofprotection.

Turbo Product Codes Construction

Two-dimensional (2D) TPCs are constructed by serially concatenating twolinear block codes C^(i) (i=1, 2). The two component codes C^(i), alsoreferred to as elementary codes, have the parameters (n_(i), k_(i),d_(min) ^(i)) which describe the codeword length, number of informationbits, and minimum Hamming distance, respectively. To build a productcode, k₁×k₂ information bits are placed in a matrix of k₁ rows and k₂columns. The k₁ rows are encoded by code C¹ and a matrix of size k₁×n₁is generated. Then, the n₁ columns are encoded by the C² code and atwo-dimensional codeword of size n₂×n₁ is obtained. The parameters ofthe product code C are (n₁×n₂, k₁×k₂, d_(min) ⁽¹⁾×d_(min) ⁽²⁾). The coderate which is the number of information bits divided by the codewordsize is calculated as ζ=((k₁×k₂)/(n₁×n₂)) for regular TPCs. FIG. 1 showsan illustration of a TPC codeword. When n₁=n₂

n, k₁=k₂

k and d_(min) ⁽¹⁾=d_(min) ⁽²⁾

d_(min), a square product code is constructed, denoted as (n, k,d_(min))².

TPCs can be constructed using different component codes such as Hammingcodes, Bose-Chaudhuri-Hocquenghem (BCH) codes, Reed-Solomon (RS) codes,and LDPC codes.

Near-Optimal Iterative Decoding of TPCs

This section surveys existing literature on TPCs iterative decodingtechniques where hard and soft decision decoding methods are described.Turbo product codes are powerful FEC codes that can provide high codinggain. Nevertheless, the complexity of TPCs decoders can be very highwhen maximum likelihood decoding (MLD) is used. Therefore, sub-optimumiterative decoding methods are alternatively used to reduce thecomplexity while providing satisfactory performance. Assuming thetransmission of binary phase shift keying (BPSK) symbols over an AWGNchannel, a transmitted TPC codeword U is received as R=U+Z where Z is amatrix of AWGN samples with zero mean and N₀/2 variance. If harddecision decoding (HDD) is desired, the matrix R is converted to abinary matrix B that is fed to the TPC decoder, where B=0.5(sign[R]+1)and sign(.) is the signum function. Otherwise, R is fed directly to thedecoder for soft decision decoding (SDD).

Near-optimum decoding of TPCs is achieved by performing a number ofsoft-input soft-output (SISO) iterative decoding processes. In the firststep, the TPC matrix is partitioned into smaller row/column vectorswhich are individually decoded using a soft decision iterative decodingalgorithm. During the first half iteration, actual soft information isavailable from the demodulator; however, extrinsic information is usedin the succeeding iterations. The SDD is implemented using the Chase-IIdecoder, which performs a limited search for the maximum likelihoodcomponent code word instead of a prohibitively complex exhaustivesearch. The search process can be described as follows:

-   -   a) The least reliable p bits in b=(b₁, b₂, . . . , b_(n)), a        row/column in B, are marked using r=(r₁, r₂, . . . , r_(n)), a        row/column in R. In stationary AWGN channels, the normalized        reliability is given by |r_(i)|.    -   b) 2^(p) different error patterns are generated using the marked        p bits in b. An error pattern is a vector whose entries are all        zeros except the entries marked in the previous step.    -   c) 2^(p) different error patterns are generated by altering the        values of the marked p bits.    -   d) 2^(p) different test patterns are generated by adding each        error pattern to b. Each of the 2^(p) test patterns is decoded        using HDD to produce 2^(p) candidate codewords. The successful        candidate codeword d is the one that has the minimum Euclidean        distance to r. Therefore, the number of HDDs performed in each        iteration is 2^(p) (n₁+n₂).    -   e) Once the first half iteration is completed, the Chase-II        decoder output is the binary vector d; hence, we still need to        generate soft information for each bit in d to enable SDD for        the next iterations. Note that the elements of d are mapped from        {0, 1} to {−1, +1}. The soft information after the first        iteration is calculated using        {tilde over (r)}(m)=r+α(m)w(m)  (1)        where {tilde over (r)}(m) is the soft data fed to the Chase-II        decoder at the mth iteration, r is the demodulator soft output,        α(m) is a scaling factor obtained experimentally, and w(m) is        the extrinsic information calculated from the previous        iteration. Extrinsic information is computed as        w(m+1)=ŕ(m)−{tilde over (r)}(m)  (2)        where

$\begin{matrix}{{{\overset{\prime}{r}}_{i}(m)} = {\frac{1}{4}\left( {{{r - d^{(2)}}}^{2} - {{r - d^{(1)}}}^{2}} \right) \times {d_{i}}^{(1)}}} & (3)\end{matrix}$|x−y|²=Σ_(i)|x_(i)−y_(i)|², d⁽¹⁾ and d⁽²⁾ are the closest and nextclosest candidate codewords to r, respectively. For each bit i in ŕ(m),d⁽²⁾ is chosen such that d²≠d¹ at the ith bit, i∈{1, 2, . . . , n}. Incases where it is not possible to find d⁽²⁾ we usew _(i)(m)=β(m)×d _(i), β≥0  (4)where β is also a scaling factor. The values of α and β for 8 halfiterations (m∈{1, 2, . . . , 8}) are given in:α=[0.0,0.2,0.3,0.5,0.7,0.9,1.0,1.0]  (5)andβ=[0.2,0.4,0.6,0.8,1.0,1.0,1.0,1.0]  (6)

Entries in the extrinsic information matrix computed using (2) arenormalized to have a mean absolute value of one. FIG. 2 shows a generalblock diagram for Pyndiah-Chase-II decoder.

Low complexity iterative decoding can be achieved using hard-inputhard-output (HIHO) decoding. HIHO is similar to SISO in terms of theiterative operations, however, each row/column in the matrix B isdecoded using a single HDD operation. HIHO has very low complexity anddelay, but at the expense of modest coding gain.

The New Ultra-Light Decoder (ULD)

In conventional SD decoding, the Chase-II decoder is used to perform thesoft decision decoding, where each row and column in the received matrixhas to go through HDD for 2^(p) times at each SDD operation. Therefore,the SISO complexity becomes much higher than HIHO, which requires onlyone HDD operations. Nevertheless, the SDD when combined with TPCprovides spectacular coding gain as compared to the HDD. To overcome thecomplexity problem of TPC decoding, we propose an efficient SDD that canbe used in TPC decoders.

Assume that u is codeword generated by the linear block code C withparameters (n, k, d_(min)). Given that the generator matrix for C is G∈

^(n×n), thenu=m×G  (7)where u=[m₁, m₂, . . . , m_(k), p₁, p₂, . . . p_(n-k)], m_(i) and p_(j)correspond to the information and parity bits, respectively. Assumingthat u is BPSK modulated, and transmitted over an AWGN channel, then thereceived vector r can be expressed as r=u+z, where z is the AWGN vector.Then, the new SDD process can be applied as follows:

-   -   a) Drop the last n−k samples in r, which correspond to the        parity bits. The new vector becomes r_(1→k).    -   b) Mark the indices (locations) of the least reliable q samples        in r_(1→k). For AWGN channels, the reliability of the ith sample        is equal to |r_(i)|.    -   c) Compute the hard decision bits of r_(1→k) such that

$b = {\frac{1}{2}{\left( {{{sign}\left( r_{1->k} \right)} + 1} \right).}}$

-   -   d) Generate 2^(q) vectors (error patterns) each of which has k        bits, e_(i)=[e₁, e₂, . . . , e_(k)], i∈{0, 1, . . . , 2^(q)−1}.        An error pattern is a vector whose entries are all zeros except        the entries marked in the previous step. The values of the        marked bits will be altered between zeros and ones until all        possible 2^(q) combinations are generated.    -   e) Generate 2^(q) different test patterns by adding each error        pattern to b, t_(i)=e_(i)⊕b.    -   f) Each of the 2^(q) test patterns is then encoded by computing        ũ_(i)=t_(i)×G to produce 2^(q) candidate codewords. The        successful candidate codeword d is the one that has the minimum        Euclidean distance to r,

$\begin{matrix}{{d = {\arg{\underset{t_{i}}{\;\min\;}{{r - {\overset{\sim}{u}}_{i}}}^{2}}}},{i = \left\lbrack {0,1,\ldots\;,{2^{q} - 1}} \right\rbrack}} & (8)\end{matrix}$

-   -   g) As it can be noted from the described algorithm, no HDD        operations are needed to generate the candidate codewords. Once        the first half iteration is completed, we generate soft        information for each bit in d to enable SDD for the next        iterations. Note that the elements of d are mapped from {0, 1}        to {−1, +1}. The soft information after the first iteration is        calculated using (1). To compute (1), the extrinsic information        can be computed as

$\begin{matrix}{{w\left( {m + 1} \right)} = \frac{{\overset{\prime}{r}(m)} - {\overset{\sim}{r}(m)}}{{{{\overset{\prime}{r}(m)} - {\overset{\sim}{r}(m)}}}_{\infty}}} & (9)\end{matrix}$where the max norm ∥x∥_(∞)=max(|x₁|, |x₂|, . . . , |k_(n)|),

$\begin{matrix}{{\overset{\prime}{r}(m)} = {\frac{1}{4}\left( {{{r - d^{(2)}}}^{2} - {{r - d^{(1)}}}^{2}} \right) \times d^{(1)}}} & (10)\end{matrix}$and d⁽¹⁾ and d⁽²⁾ are the closest and next closest candidate codewordsto r, respectively. Note that in (10) all bits in ŕ(m) have the samesoft value. In cases where it is not possible to find d⁽²⁾ we use (4).

The values of α and β for 8 half iterations (m∈{1, 2, . . . , 8}) areα=[0.0 0.0 0.2 0.2 0.3 0.3 0.5 0.5]  (11)andβ=[0.2 0.2 0.4 0.4 0.6 0.6 0.8 0.8].  (12)

The SDD and soft output generation are applied to all rows/columns in asimilar fashion to the conventional SISO decoding, till the maximumnumber of iterations is reached.

Numerical Examples

To evaluate the performance of the new ULD, we use bit error rate (BER)as a metric and compare the results with near optimal SISO (˜Optimal)and HIHO decoding. The BER for all systems is obtained using Monte Carlocomputer simulation. The channel is modeled as an AWGN channel, and theinformation bits are modulated using BPSK. The proposed and near-optimaldecoders are using p=q=4, and the maximum number of iterations is fourin all types of decoders.

The BER of the eBCH(16,11,4)² is shown FIG. 3. As it can be noted fromthe figure, the ULD coding gain of 5.8 dB at BER=10⁻⁵, which is only 0.8dB less than the coding gain of the near-optimal decoder.

FIG. 4 shows the BER of the eBCH(32,26,4)² TPC code. For this code, thenew ULD has a gain of 5.4 dB at BER=10⁻⁵, which is about 1.1 dB lessthan the coding gain of the near-optimal decoder. Moreover, the ULDcoding gain advantage over the HIHO decoder is about 2.7 dB.

FIG. 5 and FIG. 6 shows the BER of the eBCH(64,57,4)² andeBCH(128,120,4)² codes, for both codes, the ULD showed a significantcoding gain over the HIHO decoder and about 1 dB coding gain less thanthe near-optimal decoder at BER=10⁻⁵.

Therefore, the new ULD is highly efficient because its coding gain iswithin 1 dB from the near-optimum decoder. However, the complexity ofthe proposed system is substantially less due to the elimination of theHDD operation at the decoder side, and replacing them by a simpleaddition process similar to the one performed at the encoder.

The speed of the ULD is compared to the near-optimal decoder using therelative simulation time (RST) per iteration, where the RST is definedas the simulation time of the proposed system divided by the simulationtime of the near-optimal decoder. As it can be noted in Table 1, the RSTcan be as low as 22%, which implies that the proposed ULD decoding timeis well below the conventional system.

TABLE 1 Relative simulation time of four different TPC codes.eBCH(16,11,4)² eBCH(32,26,4)² eBCH(64,57,4)² eBCH(128,120,4)² RST 22.01%26.90% 37.09% 56.83%

Conclusion

In this patent application, there is provided an efficient decoder whichcan be used for turbo product codes. The new decoder is highly efficientdue the elimination of the hard decision decoding process used inconventional turbo decoders. In addition to the substantial complexityreduction, the new decoder will be much faster than other decoders, andhence will reduce the delay and buffering requirements at the receiver.Moreover, the error correction capability of the new decoder iscomparable to the near-optimal decoder where the losses are only aboutone dB in terms of coding gain at bit error rate of 10⁻⁵.

The foregoing descriptions of specific embodiments of the presentinvention have been presented for purposes of illustration anddescription. They are not intended to be exhaustive or to limit thepresent invention to the precise forms disclosed, and obviously manymodifications and variations are possible in light of the aboveteaching. The embodiments were chosen and described in order to bestexplain the principles of the present invention and its practicalapplication, and to thereby enable others skilled in the art to bestutilize the present invention and various embodiments with variousmodifications as are suited to the particular use contemplated. It isunderstood that various omissions and substitutions of equivalents arecontemplated as circumstances may suggest or render expedient, but suchomissions and substitutions are intended to cover the application orimplementation without departing from the spirit or scope of the presentinvention.

The invention claimed is:
 1. An improved soft decision decoder for digital communications configured to decode a received signal (r) using an improved soft decision decoding process, wherein the improved soft decision decoding process comprises: a) dropping parity data in the received signal (r) for forming a new vector r_(1→k), where the new vector r_(1→k) comprises least reliable q samples having respective indices; b) determining the least reliable q samples in the new vector r_(1→k), and marking the indices of the least reliable q sample in r_(1→k) (marked bits); c) computing binary decision bits of r_(1→k); d) generating 2^(q) vectors (error patterns) each of which has k bits by alternating values of the marked bits between zeros and ones until all possible 2^(q) combinations are generated; e) generating 2^(q) different test patterns by adding each error pattern to the binary decision bits computed in (c); f) encoding 2^(q) test patterns to produce 2^(q) candidate codewords; and g) determining a successful candidate codeword among the produced 2^(q) candidate codewords, where the successful candidate is one that has a minimum Euclidean distance to the received signal (r).
 2. The improved soft decision decoder as claimed in claim 1 wherein the improved soft decision decoder does not include a Hard Decision Decoding (HDD) decoder and the decoding process does not involve any Hard Decision Decoding (HDD) operations.
 3. The improved soft decision decoder as claimed in claim 2, wherein the block coding is turbo coding.
 4. The improved soft decision decoder as claimed in claim 3, wherein the received signal (r) is an analog signal comprising a transmitted signal (u) and channel noise (z) such that r=u+z, where the transmitted vector (u) comprises information data and parity data expressed by u=[m₁, m₂, . . . , m_(k), p₁, p₂,. . . , p_(n-k)], where m_(i) and p_(j) correspond to the information data and parity data respectively.
 5. The improved soft decision decoder as claimed in claim 4, wherein the received signal (r) is encoded using block coding, modulated using a modulation technique and transmitted over a communication channel subject to channel noise, wherein the improved soft decision decoder comprises a block encoder configured to encode data as part of the improved soft decision decoding process, to reduce delay and buffering requirements at a receiver.
 6. The improved soft decision decoder as claimed in claim 5, wherein the channel noise is Additive White Gaussian Noise (AWGN).
 7. The improved soft decision decoder as claimed in claim 6, wherein the modulation technique is binary phase-shift keying (BPSK).
 8. A receiver comprising an improved soft decision decoder for digital communications configured to decode a received signal (r) using an improved soft decision decoding process, the improved soft decision decoding process comprising the steps of: a) dropping parity data in the received signal (r) for forming a new vector r_(1→k), where the new vector r_(1→k) comprises least reliable q samples having respective indices; b) determining the least reliable q samples in the new vector r_(1→k), and marking the indices of the least reliable q sample in r_(1→k) (marked bits); c) computing binary decision bits of r_(1→k); d) generating 2^(q) vectors (error patterns) each of which has k bits by alternating values of the marked bits between zeros and ones until all possible 2^(q) combinations are generated; e) generating 2^(q) different test patterns by adding each error pattern to the binary decision bits computed in (c); f) encoding 2^(q) test patterns to produce 2^(q) candidate codewords; and g) determining a successful candidate codeword among the produced 2^(q) candidate codewords, where the successful candidate is one that has a minimum Euclidean distance to the received signal (r).
 9. The receiver as claimed in claim 8 wherein the improved soft decision decoder does not include a Hard Decision (HD) decoder and the decoding process does not involve any Hard Decision Decoding (HDD) operations.
 10. The improved soft decision decoder as claimed in claim 9, wherein the block coding is turbo coding.
 11. The receiver as claimed in claim 10, wherein the received signal (r) is an analog signal comprising a transmitted signal (u) and channel noise (z) such that r=u+z, where the transmitted vector (u) comprises information data and parity data expressed by u=[m₁, m₂, . . . , m_(k), p₁, p₂, . . . p_(n-k)], where m_(i) and p_(j) correspond to the information data and parity data respectively.
 12. The receiver as claimed in claim 11, wherein the received signal (r) is encoded using block coding, modulated using a modulation technique and transmitted over a communication channel subject to channel noise, wherein the improved soft decision decoder comprises a block encoder configured to encode data as part of the improved soft decision decoding process, to reduce delay and buffering requirements at the receiver.
 13. The receiver as claimed in claim 12, wherein the channel noise is Additive White Gaussian Noise (AWGN).
 14. The receiver as claimed in claim 13, wherein the modulation technique is binary phase-shift keying (BPSK).
 15. An improved soft decision decoding process for decoding a received signal (r), the improved soft decision decoding process comprising: a) dropping parity data in the received signal (r) for forming a new vector r_(1→k), where the new vector r_(1→k) comprises least reliable q samples having respective indices; b) determining the least reliable q samples in the new vector r_(1→k), and marking the indices of the least reliable q sample in r_(1→k) (marked bits); c) computing binary decision bits of r_(1→k); d) generating 2^(q) vectors (error patterns) each of which has k bits by alternating values of the marked bits between zeros and ones until all possible 2^(q) combinations are generated; e) generating 2^(q) different test patterns by adding each error pattern to the binary decision bits computed in (c); f) encoding 2^(q) test patterns to produce 2^(q) candidate codewords; and g) determining a successful candidate codeword among the produced 2^(q) candidate codewords, where the successful candidate is one that has a minimum Euclidean distance to the received signal (r).
 16. The improved soft decision decoding process as claimed in claim 15 wherein the improved soft decision decoding process does not involve any Hard Decision Decoding (HDD) operations.
 17. The improved soft decision decoding process as claimed in claim 16, wherein the block coding is turbo coding.
 18. The improved soft decision decoding process as claimed in claim 17, wherein the received signal (r) is an analog signal comprising a transmitted signal (u) and channel noise (z) such that r=u+z, where the transmitted vector (u) comprises information data and parity data expressed by u=[m₁, m₂, . . . , m_(k), p₁, p₂, . . . , p_(n-k)], where m_(i) and p_(j) correspond to the information data and parity data respectively.
 19. The improved soft decision decoding process as claimed in claim 18, wherein the received signal (r) is encoded using block coding, modulated using a modulation technique and transmitted over a communication channel subject to channel noise, wherein the improved soft decision decoding process comprises encoding data using a block encoder as part of the improved soft decision decoding process, to reduce delay and buffering requirements at a receiver.
 20. The improved soft decision decoding process as claimed in claim 19, wherein the channel noise is Additive White Gaussian Noise (AWGN), and the modulation technique is binary phase-shift keying (BPSK). 